Minimum Cost Layout Decomposition and Legalization for Triple Patterning Lithography

نویسندگان

  • Wenxing Zhu
  • Xingquan Li
  • Ziran Zhu
چکیده

With the need of 16/11nm cells, triple patterning lithography (TPL) has been concerned in lithography industry. Basing on a new projection method for identifying conflicts, we solve the TPL layout decomposition problem in two steps. First, we formulate in this paper the TPL layout decomposition problem as a minimum cost coloring problem, and it is relaxed to a nonlinear 0-1 programming problem. Second, legalization methods are introduced to legalize a solution of the nonlinear 0-1 programming problem to a feasible one. At the legalization step, we prior utilize one-stitch insertions to eliminate conflicts. For very few independent components, a backtrack coloring algorithm is also used at this step to obtain a better relaxation coloring solution. At last, to improve scalability of our decomposition method, two graph reduction methods are adopted. We test our decomposition approach on the ISCAS-85 & 89 benchmarks. Comparisons of experimental results show that our approach achieves optimal costs better than those of state-ofthe-art decomposers. Moreover, our decomposition approach is faster than most of the decomposers on the tested benchmarks.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Layout Compliance for Triple Patterning Lithography: An Iterative Approach

As the semiconductor process further scales down, the industry encounters many lithography-related issues. In the 14nm logic node and beyond, triple patterning lithography (TPL) is one of the most promising techniques for Metal1 layer and possibly Via0 layer. As one of the most challenging problems in TPL, recently layout decomposition efforts have received more attention from both industry and...

متن کامل

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session)

Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently, as an alternative process, triple patterning lithography with end cutting (LELE-EC) was proposed to overcome the limitations of LELELE manufacturing. In LELE-EC process the first tw...

متن کامل

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting

Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout dec...

متن کامل

Layout Decomposition for Triple Patterning

Layout decomposition is a key stage in triple patterning lithography manufacturing process, where the original designed layout is divided into three masks. There will be three exposure/etching steps, through which the circuit layout can be produced. When the distance between two input features is less than certain minimum distance mins, they need to be assigned to different masks (colors) to av...

متن کامل

Triple patterning lithography layout decomposition using end-cutting

Triple patterning lithography (TPL) is one of the most promising techniques in the 14-nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently, as an alternative process, TPL with end-cutting (LELE-EC) was proposed to overcome the limitations of LELELE manufacturing. In the LELE-EC process, the first two masks are LELE typ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2015